USB 3.0 Gen1 / Gen2 Device Controller IP
function drivers to be implemented easily. Reference mass storage class device-side function drivers are also available to all licensees. All buffering associated with the DMA Engine are configurable based on latency and performance requirements.
The USB 3.0 device controller can include an proprietary EP0 processor block for managing all standard requests directed to the control endpoint, minimizing software development overheads. Class and vendor specific requests directed to the control endpoint are routed to the software via the DMA engine, for processing. Optionally, the controller can be provided with no DMA Engine and no buffering. This operates in a cut-through mode, forwarding and receiving USB payloads and managing only the USB protocol. In this case, the customer may implement their own differentiated DMA engine. A simple transmit and receive buffer is also included in this configuration which, accessible by software over the slave register access interface (typically AHB). This option results in very low-footprint hardware which can be used where the software can completely manage the USB traffic including USB transactions sequencing.
View USB 3.0 Gen1 / Gen2 Device Controller IP full description to...
- see the entire USB 3.0 Gen1 / Gen2 Device Controller IP datasheet
- get in contact with USB 3.0 Gen1 / Gen2 Device Controller IP Supplier
Block Diagram of the USB 3.0 Gen1 / Gen2 Device Controller IP

USB IP IP
- USB 3.0 femtoPHY in TSMC (28nm, 16nm, 12nm)
- USB 3.0 femtoPHY, Type-C in TSMC (28nm, 16nm, 12nm)
- USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
- USB 3.1 PHY (10G/5G) in TSMC (16nm, 12nm, 7nm, 5nm)
- Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP
- Complete USB Type-C Power Delivery PHY, RTL, and Software