The USB 3.0 Host controller is a highly configurable core and implements the USB 3.0 Host functionality that can be interfaced with third party USB 3.0 PHY's. The Host Controller core is architected with an optional high performance DMA engine based on xHCI specification. The core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.
The Host Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications. The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.
The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and most importantly, the target technology. GDA solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally.
Block Diagram of the USB 3.0 Host controller IP Core