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PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
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USB 3.0 PCIe 2.0 SATA 3.0 Combo PHY IP, Silicon Proven in SAMSUNG 8LPP
The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of PIPE interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control.
Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.
Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.
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