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USB 3.0 PCIe 2.0 SATA 3.0 Combo PHY IP, Silicon proven in SMIC 40LL
USB 3.0 PCIe 2.0 SATA 3.0 Combo PHY IP is a high performance SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption. Combo PHY IP support multiple application including USB3.0 Super Speed (5GT/s), PCIE Gen1/Gen2 (2.5GT/s and 5GT/s) and SATA Gen1/Gen2/Gen3 (1.5GT/3GT/6GT). This also includes PMA IP with maximum 6.Gbps data rate macro that can be used in other
applications. This IP includes two major blocks, PMA and PCS. PMA is an analog macro to perform serial to parallel and parallel to serial conversion. PMA includes three blocks, Transmitter, Receiver and SU (includes PLL, IVREF, etc.). PCS is a digital synthesis macro to perform PHY coding sub-layer function like 8bit/10bit, elastic buffer, comma detection and BERT loopback, it also includes a register interface to access internal control registers.
applications. This IP includes two major blocks, PMA and PCS. PMA is an analog macro to perform serial to parallel and parallel to serial conversion. PMA includes three blocks, Transmitter, Receiver and SU (includes PLL, IVREF, etc.). PCS is a digital synthesis macro to perform PHY coding sub-layer function like 8bit/10bit, elastic buffer, comma detection and BERT loopback, it also includes a register interface to access internal control registers.
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