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USB 3.0 PHY Device/Host/OTG/Hub UMC 40LP

The INNOSILICON USB 3.0 PHY is fully spec compliant. Combining the efficiency of a mature, but compact, USB 3.0 PHY with a Super Speed PHY to provide 5Gb/s operation, this complete solution is the answer to your USB 3.0 needs. Streamlined production testing is supported through BIST, multiple loopback modes and boundary scan. Its modular nature is flexible, ensuring a PHY combination that is able to support the latest in C-type connector configurations while including all the I/Os, ESD in a single drop-in block. As with all Innosilicon IP, our USB 3.0 solution is fully customizable to meet your specific needs.

Features

Supports 5.0Gb/s serial data transmission rate Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive USB SuperSpeed data
Allows integration of high speed components into a single functional block as seen by the device designer.
Data and clock recovery from serial stream on the USB SuperSpeed bus
Holding registers to stage transmit and receive data
Supports direct disparity control for use in transmitting compliance pattern
8b/10b encode/decode and error indication
Receiver detection
Low Frequency Periodic Signaling ( LFPS) Transmission
Selectable Tx Margining

Benefits

As with all Innosilicon IP, the focus is on silicon proven, fully certified solutions providing:
Small size
Low power
High ATE coverage
Simple integration
Flexible customization

Deliverables

We can provide the following deliverables to aid quick and reliable integration into the design flow. Please contact us for any additional views:
GDSII
Netlist (Spice format for LVS)
Footprint (LEF format)
User documentation
Module integration guidelines
Datasheet
Silicon validation report
Evaluation board

Applications

Application processor interfaces
PCB Embedded devices

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