English
You are here:
USB 3.0 PHY in SMIC (110nm, 65nm, 40nm, 28nm)
Synopsys' DesignWare USB-C 3.0 and USB 3.0 PHY IP provide designers with the industry's best combination of low area and low power with support for the leading process technologies from 65-nm to 14/16-nm FinFET. Both the DesignWare USB-C and USB 3.0 PHYs offer a single efficient GDSII design that supports all four USB 3.0 speed modes (SuperSpeed, High-Speed, Full-Speed, and Low-Speed). To maximize battery life in mobile applications, the DesignWare USB-C/USB 3.0 PHYs are designed to minimize power consumption and standby current. In addition, the DesignWare USB-C 3.0 femtoPHY is optimized to support the USB Type-C connectivity specification.
Synopsys DesignWare USB IP is the most certified USB IP solution in the industry. With over 3,000 design wins and approximately three billion silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHYs, verification IP, IP Prototyping Kits and IP software development kits, enables designers to lower integration risk and speed time-to-market.
Synopsys DesignWare USB IP is the most certified USB IP solution in the industry. With over 3,000 design wins and approximately three billion silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHYs, verification IP, IP Prototyping Kits and IP software development kits, enables designers to lower integration risk and speed time-to-market.
Features
- Single efficient GDSII design supports all four USB 3.0 speed modes (SuperSpeed, High-Speed, Full Speed, and Low Speed)
- USB-C 3.0 IP reduces pin count up to 40% for Type-C connections
- USB 3.0 femtoPHY on 14/16-nm FinFET and 28-nm processes offers 50% smaller area use, high
- performance, and advanced power features
- Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD
- Supports SuperSpeed USB power savings modes, UPF, and Synopsys-specific features to maximize
- battery life
- Design minimizes area and power
- High yield: Designed to improve key operating margins by having less sensitivity to variations due to foundry process, chip and board parasitics, and process device variations
Benefits
- Supports SuperSpeed USB (USB 3.0) and High-Speed USB (USB 2.0)
- DesignWare USB-C™ 3.1 PHY optimized for USB Type-C connectivity and USB specifications
- Dual Role Device (DRD), Host, and Device controllers provide the full range of USB features
- Supports PIPE, UTMI+ and ULPI PHY interfaces
- Architectural features reduce power consumption
- SuperSpeed USB logo-certified controllers and PHYs
- SuperSpeed USB IP offering from the #1 provider of USB IP for thirteen years in a row (Gartner 2015)
Deliverables
- GDSII layout and layer map files
- Simulation model for digital circuits
- Behavioral models for analog circuits
- Synopsys’ PrimeTime® Static Timing Analysis results
- Design Rule Check (DRC) report
- LVS netlist and SDF timing files
- Comprehensive databook
Applications
- Smartphones
- Tablets, ultrabooks, netbooks
- Gaming
- Digital cameras and camcorders
- Storage
- Wireless communication
- Set-top boxes
- Smart TVs and digital TVs
- Chip-to-chip low-power interconnects
View USB 3.0 PHY in SMIC (110nm, 65nm, 40nm, 28nm) full description to...
- see the entire USB 3.0 PHY in SMIC (110nm, 65nm, 40nm, 28nm) datasheet
- get in contact with USB 3.0 PHY in SMIC (110nm, 65nm, 40nm, 28nm) Supplier