USB 3.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 28HPC+)
The USB3.0 PHY IP transceiver is optimized for low power consumption and minimal die area without sacrificing performance and high-data throughput. The USB3.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs.
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Block Diagram of the USB 3.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 28HPC+)

USB 3.0PHY IP
- USB 3.1 PHY IP ((10G/5G),Silicon proven in SMIC 14SF+/ SF++)
- USB 3.2 PHY IP ((20G/10G),Silicon proven in UMC 28HPC+)
- USB 3.1 PHY IP ((10G/5G),Silicon proven in TSMC 28HPC+)
- USB 3.0 PHY IP Device/Host/OTG/Hub (Silicon proven in UMC 40LP)
- USB 3.1 PHY IP ((10G/5G),Silicon proven in UMC 28HPC+)
- USB 3.0 PHY IP Device/Host (Silicon proven in UMC 28HPC)