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USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm, 6nm)
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USB 3.0 PHY IP Device/Host (Silicon proven in UMC 28HPC)
The USB3.0 IP is a highly integrated and cost-effective IP. It contains a USB3.0 PHY and a USB2.0 PHY. The USB3.0 PHY is used for Super-Speed (SS) transfers and the USB2.0 PHY is used for High-Speed (HS), Full-Speed (FS), and Low-Speed (LS) transfers. The USB3.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs. The USB3.0 PHY IP consists of both the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and connects easily to either the USB MAC layer using the standard PIPE-3.0 interface.
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USB 3.0PHY IP
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