The USB 3.0 SSIC controller is a highly configurable core and implements the USB 3.0 SSIC functionality that can be interfaced with third party M-PHY's. The SSIC Controller core is architected to seamlessly integrate with either in-house developed SS Host/Device Controller cores or with standard 3rd party SS Host/Device Controller cores. It is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.
The controller when integrated with in-house Device/xHCI Host controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as
AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.
- Application Interface – AHB, AXI, PCIe-MPHY
- Optional xHCI Engine with configurable number of device
- slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc
- Optional Device Controller with configurable number of Endpoints,
- Types, DMA Engine and EP0 Processor
- Number RMMI Lanes support