USB 3.0 SSIC Controller
The controller when integrated with in-house Device/xHCI Host controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as
AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.
Configurable Options
- Application Interface – AHB, AXI, PCIe-MPHY
- Optional xHCI Engine with configurable number of device
- slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc
- Optional Device Controller with configurable number of Endpoints,
- Types, DMA Engine and EP0 Processor
- Number RMMI Lanes support
Features
- Compliant with SSIC v1.01
- Compliant with M-PHY Specification v2.0
- Compliant with USB3.0 Pipe Specification.
- Supports Type I M-PHY Port.
- Supports 1/2/4 M-PHY Lanes.
- Supports PWM-G1, HS-G1/G2/G3 Rate A/B series.
- Implements PHY adaptor which bridges between RMMI and USB 3.0 Pipe.
- Asynchronous clocking USB 3.0 Controller and RMMI Bridging Layer.
- Configurable USB 3.0 PIPE Interface: 8, 16, 32 bit.
- Configurable RMMI Interface width: 8, 16, 32-bit.
- Supports Aggressive Low Power Management.
- Can seamlessly integrate with 3rd Party USB 3.0 Host/Device Controller cores.
- Can integrate with in-house USB 3.0 Host/Device Controller to expose flexible User
- Application Logic
- Can be adapted by any SoC / OCB interface / offchip interconnects – such as AHB, AXI, PCIe
- Configurable Datawidth: 32, 64, 128 bit.
- Simple Register Interface for internal Register Access.
- Support for various Hardware and Software Configurability regarding Core characteristics.
Benefits
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Extensive clock gating support
- Multiple Power Well Support
- Software control for key features
- Multiple loop backs for debug
Deliverables
- Configurable RTL Code
- HDL based test bench and behavioral models Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
Block Diagram of the USB 3.0 SSIC Controller IP Core

View USB 3.0 SSIC Controller full description to...
- see the entire USB 3.0 SSIC Controller datasheet
- get in contact with USB 3.0 SSIC Controller Supplier