USB 3.1 Gen1 / Gen2 Device Controller IP
This Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.
This controller has a very simple application interface which can be
easily adapted to standard on-chip-bus interfaces such as AXI,
AHB, OCP as well as other standard off-chip interconnects making
it easy to be integrated in a wide range of applications.
The Controller also has a dedicated PHY Type-C connector Interface for identifying Type-C specific features such as cable orientation, ID function based on Configuration data channel etc.
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Block Diagram of the USB 3.1 Gen1 / Gen2 Device Controller IP

USB IP IP
- USB 3.0 femtoPHY in TSMC (28nm, 16nm, 12nm)
- USB 3.0 femtoPHY, Type-C in TSMC (28nm, 16nm, 12nm)
- USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
- USB 3.1 PHY (10G/5G) in TSMC (16nm, 12nm, 7nm, 5nm)
- Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP
- Complete USB Type-C Power Delivery PHY, RTL, and Software