USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+

With this PHY IP, it supports both USB 3.1 Gen1 and Gen2. By providing an integrated self-test module, a whole on-chip physical transceiver solution with built- in jitter injection, and ESD protection (ESD). This USB 3.1 Gen2 PHY IP implements a USB 3.1 Gen2 transceiver and can be used as a host or device. PHY IP features an integrated mixed signal circuit and supports USB 3.1 Gen2 high speed data rates up to 10Gbps as well as Gen1 5Gbps data rate.

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