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400MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
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USB 3.2 Gen1X1 PHY IP in TSMC(7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm, 65nm)
M31 USB3.2 Gen1X1 transceiver IP provides a complete range of USB3.2 Gen1X1 host and peripheral applications. It is compliant with the PIPE 4.0 and UTMI+ specification. The USB3.2 Gen1X1 IP integrates high-speed mixed signal circuits to support super-speed traffic at 5Gbps and is backward compatible to high-speed data rate at 480Mbps, full-speed data rate at 12Mbps and low-speed data rate at 1.5Mbps.
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superspeed USB 3.2 Gen1X1 PHY IP
- USB 3.2 Gen1 / Gen2 Device Controller IP
- USB-C 3.2 SS/SSP PHY, Type-C in TSMC (7nm, 5nm)
- USB-C 3.2 SuperSpeed/SuperSpeedPlus PHY IP in TSMC N6
- USB 3.2 OTG High / Full / Low- Speed Dual Role IP Core
- USB 3.2 High/Full/Low-Speed Host + Device Controller IP
- USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 28HPC+)