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USB 3.2 Gen1X1 PHY IP in TSMC(7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm, 65nm)
M31 USB3.2 Gen1X1 transceiver IP provides a complete range of USB3.2 Gen1X1 host and peripheral applications. It is compliant with the PIPE 4.0 and UTMI+ specification. The USB3.2 Gen1X1 IP integrates high-speed mixed signal circuits to support super-speed traffic at 5Gbps and is backward compatible to high-speed data rate at 480Mbps, full-speed data rate at 12Mbps and low-speed data rate at 1.5Mbps.
Features
- Worldwide smallest USB3.2 Gen1X1 PHY IP in 28nm process (IP size is
- smaller than 0.5mm²)
- Fully compliant with Universal Serial Bus USB3.2 Gen1X1 and 2.0 electrical specifications
- Compliant with PIPE4.0 and UTMI+ specification (Super-Speed, High-Speed,
- Full-Speed and Low-Speed functions)
- Supports clock inputs from 25MHz crystal oscillator or external 25MHz clock source
- Provides plenty of register controls for TX, RX, SSCG-PLL and CDR electrical parameters
- Silicon proven and mass production IP records
- USB-IF certified PHY IP are available in 12nm/16nm, 28nm, 40nm, 55nm, 65nm and 110nm process
View USB 3.2 Gen1X1 PHY IP in TSMC(7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm, 65nm) full description to...
- see the entire USB 3.2 Gen1X1 PHY IP in TSMC(7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm, 65nm) datasheet
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