USB 3.2 PCIe 3.1 SATA 3.2 Combo PHY IP, Silicon proven in UMC 28HPC+
3.2 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under
View USB 3.2 PCIe 3.1 SATA 3.2 Combo PHY IP, Silicon proven in UMC 28HPC+ full description to...
- see the entire USB 3.2 PCIe 3.1 SATA 3.2 Combo PHY IP, Silicon proven in UMC 28HPC+ datasheet
- get in contact with USB 3.2 PCIe 3.1 SATA 3.2 Combo PHY IP, Silicon proven in UMC 28HPC+ Supplier