USB 3.2 PHY IP ((20G/10G),Silicon proven in UMC 28HPC+)

This PHY IP supports both USB3.2 Gen1 & Gen2.This USB 3.2 Gen2 PHY IP implements USB3.2 Gen2 transceiver and can be used as host and device. PHY IP supports USB3.2 Gen2 high speed data rate up to 20Gbps with integrated mixed signal circuit, also supports Gen1 10Gbps data rate. USB 3.2 PHY IP provides designers with the industry's best combination of low area and low power with support for the leading process technology UMC 28HPC+ process. The USB 3.2 PHY use a single efficient GDSII design that supports the SuperSpeedPlus (20 Gbps) and SuperSpeedPlus (10 Gbps) speed modes. To maximize battery life in mobile applications, the USB 3.1 PHY is designed to minimize power consumption and standby current. This USB IP is the most certified USB IP solution in the industry. The USB 3.1 PHY IP is Silicon Proven and production proven including the digital controllers and vips in different applications. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.

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