USB 4.0 Device Controller IP Core for 40Gbps performance
Initial Versions :
• A single upstream USBv4 port with no downstream port
• One Enhanced SS Device (and/or possibly One Enhanced SS Hub)
• Supports 20G USB4 (Gen 2x2) and optionally 40G (Gen 3x2).
Subsequent Versions :
• Include Enhanced SS Hub
• Include PCIe and the DP Functions.
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Block Diagram of the USB 4.0 Device Controller IP Core for 40Gbps performance
USB IP IP
- USB 3.0 femtoPHY in TSMC (28nm, 16nm, 12nm)
- USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
- USB-C 3.1/DP TX PHY in TSMC (16nm, 12nm, 7nm)
- USB 3.1 PHY (10G/5G) in TSMC (16nm, 12nm, 7nm, 5nm)
- USB-C 3.1 SS/SSP PHY, Type-C in TSMC (16nm, 12nm, 7nm)
- Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP