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PCIe Endpoint with multiple industry standard AXI Interfaces
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USB HSIC PHY in TSMC (65nm, 40nm, 28nm, 16nm)
Synopsys' DesignWare USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C connectivity in leading process technologies from 65-nm to 14/16-nm FinFET. The DesignWare USB 2.0 PHY IP products include the USB 2.0 femtoPHYs, USB 2.0 picoPHYs, USB 2.0 nanoPHYs, and USB 2.0 HSIC-LPM PHYs.
The DesignWare USB IP is the most certified USB IP solution in the industry. With over 3,000 design wins and over one billion silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHY and Verification IP, enables designers to lower integration risk and speed time-to-market.
The DesignWare USB IP is the most certified USB IP solution in the industry. With over 3,000 design wins and over one billion silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHY and Verification IP, enables designers to lower integration risk and speed time-to-market.
Features
- Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
- Supports the USB 2.0 protocol and data rate (480 Mbps)
- Supports the USB Type-C specification
- USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
- USB 2.0 PHYs support Device, Host and OTG configurations
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