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- Verilog Implementation on RTL Level
- Supports both Full Speed (12Mbps) and Low Speed (1.5Mbps).
- The Core will perform all USB enumeration in hardware
- All interface are architecture as FIFO based model.
- CRC generation and checking
- Physical Layer Interface
- Avalon Interface Compliant
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USB 3.0 femtoPHY in TSMC (28nm, 16nm, 12nm)
USB 3.0 femtoPHY, Type-C in TSMC (28nm, 16nm, 12nm)
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Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP
Complete USB Type-C Power Delivery PHY, RTL, and Software