USB-PD PHY Digital
The CT20602_RTL is a Soft Core with Verification Environment compliant to the Standardization and implemented in the FPGA of the CT20602_EVB Evaluation System.
The IP has been designed with a very high degree of modularity thus enabling our customers to purchase it in bundle, customize it for the specific application or as separate IP blocks.
The IP has been designed in order to allow professional and fast-track synthesis/ back-end on standard CMOS libraries.
It requires two Clocks: a 100KHz Low Power Clock and a 5MHz operating Clock as well as a dedicated Reset Signal.
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Block Diagram of the USB-PD PHY Digital IP Core

Video Demo of the USB-PD PHY Digital IP Core
USB Power Delivery IP
- Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- USB V3.1 Power Delivery Type-C Port Evaluation board for OTI9108 IP
- USB-PD PHY Analog Hard Macro
- MCU-Less Active Cable Interface