GDA’s USB 2.0 Host controller is a highly configurable core and implements the USB 2.0 Host functionality that can be interfaced with third party USB 2.0 PHY’s. xHCI core is architected with an high performance DMA engine based on xHCI specification. The core can be configured to support full-fledged USB 2.0 host controller based higher performance xHCI specification for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.
- Compliant with xHCI Rev1.0
- Compliant with USB Specification Rev 2.0
- Supports HS/FS/LS mode of operation.
- Asynchronous clocking between Host Controller and Application logic.
- Supports Aggressive Low Power Management
- Configurable PHY Interface: 8/16 UTMI, ULPI.
- Flexible User Application Logic
- Can be adapted by any SoC / OCB interface / offchip interconnects – such as AHB, AXI, PCIe
- Configurable Datawidth: 32, 64, 128 bit.
- Simple Register Interface for internal Register Access.
- Support for various Hardware and Software Configurability regarding Core characteristics.
- Easy migration path for Superspeed Support
- Optional USB3.0 Core for Superspeed Support
- Application Interface – AHB, AXI, PCIe
- Configurable Buffer Sizes
- xHCI Engine with configurable number of device slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Extensive clock gating support
- Multiple Power Well Support
- Software control for key features
- RTL code
- Complete Testbenches
- Complete Testsuites
- Design Guides
- Verification Guides
- Synthesis Guides