USB2.0 Host Transceiver PHY
The core’s main blocks are clock/data recovery for FS/HS, PLL, transceiver state machines, data encoder/decoder and high-speed analog transceiver as can be seen in the main block diagram above.
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Block Diagram of the USB2.0 Host Transceiver PHY IP Core

USB2.0 Host Transceiver IP
- USB 2.0 OTG On-The-Go Transceiver PHY
- USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 28HPC+)
- USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in SMIC 14SF+/ SF++)
- USB 3.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 28HPC+)
- USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
- USB 2.0 PHY IP Device/Host (Silicon proven in UMC 28HPC)