USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
It includes the following blocks:
* Analog Driver and Receiver
* PLL generate the 480MHz clock
* Clock and Data Recovery
* NRZI encoder/decoder
* Serialize / De-serialize
* Control state machine
* Integrated pull up and self-calibrated termination resistors and switches
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