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USB3.2 Gen2 Single Lane Re-Timer IP Core
OpenFive's single lane USB3.2 Gen2 Re-Timer IP is compliant to USB3.2 Appendix E Re-Timer. It includes USB3.2 Gen2 single lane PCS layer. It is validated using FPGA prototype.
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- see the entire USB3.2 Gen2 Single Lane Re-Timer IP Core datasheet
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USB3.2 Gen2 IP
- USB3.2 Gen2 Device Controller IP Core
- USB 3.2 PHY IP ((20G/10G),Silicon proven in UMC 28HPC+)
- USB3.0 DR-OTG Controller IP Core
- USB 3.0 PCIe 2.0 SATA 3.0 Combo PHY IP, Silicon proven in TSMC 22ULP
- USB 3.0 PCIe 2.0 SATA 3.0 Combo PHY IP, Silicon proven in TSMC 16FF+
- USB 3.0 PCIe 3.0 SATA 3.0 Combo PHY IP, Silicon proven in SMIC 14SF+/SF++