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USB3.2 Gen2 Single Lane Re-Timer IP Core
OpenFive's single lane USB3.2 Gen2 Re-Timer IP is compliant to USB3.2 Appendix E Re-Timer. It includes USB3.2 Gen2 single lane PCS layer. It is validated using FPGA prototype.
View USB3.2 Gen2 Single Lane Re-Timer IP Core full description to...
- see the entire USB3.2 Gen2 Single Lane Re-Timer IP Core datasheet
- get in contact with USB3.2 Gen2 Single Lane Re-Timer IP Core Supplier