HDL Design House provides a set of IP cores for reuse along with IP core customization services to meet specific customer needs. Optimized for today’s SoC designs, these IP cores are supported with full documentation, including architectural and micro architectural specifications, synthesis scripts, detailed test plans, test case definitions and test bench descriptions. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.