400MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits
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Via1 ROM Compiler IP
- CSMC 0.18um 90% shrunk Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- UMC 55nm ULP/LowK Process via1 ROM compiler well bias
- UMC 0.11um BCD High Voltage Process Synchronous Via1 Programmable ROM Compiler
- HJTC 0.11um uLL/pFlash via1 ROM memory compiler.
- UMC 65nm Low Power/LowK Logic Process standard synchronous Via-1 programmable ROM memory compiler.
- TSMC 55nm LP Logic Process standard synchronous high density via-1 ROM compiler