English
You are here:
VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits
VeriSilicon GSMC 0.18um Synchronous Programmable Low Power Via1 ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic/Analog 1P6M Industry Baseline Generic (IBG) 1.8/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands. The compiler supports a comprehensive range of word length and bit length. While satisfying Low Power and speed requirements, it has been optimized for area efficiency. VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM compiler uses three metal layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
Features
- Low Power
- High Density
- Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time
- Automatic Power Down
View VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits full description to...
- see the entire VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits datasheet
- get in contact with VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits Supplier
Via1 ROM Compiler IP
- CSMC 0.18um 90% shrunk Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- UMC 55nm ULP/LowK Process via1 ROM compiler well bias
- UMC 40nm uLP process ULL Via1 ROM compiler
- HJTC 0.11um uLL/pFlash via1 ROM memory compiler.
- UMC 65nm Low Power/LowK Logic Process standard synchronous Via-1 programmable ROM memory compiler.
- TSMC 55nm LP Logic Process standard synchronous high density via-1 ROM compiler