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VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2/2.5V process. This library provides 5V analog IO pads. This library supports Device Under Pad (DUP).
Features
- SMIC 0.13um Logic 1P8M Salicide 1.2/2.5V process
- Provides 5V analog IO pads
- Supports Device Under Pad (DUP)
- Provides cells to interface with Generic IO library
- Suitable for six, seven, or eight metal layers of physical design
Deliverables
- Databook in electronic form
- Verilog models and Synopsys synthesis models
- Cadence Silicon Ensemble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
View VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library full description to...
- see the entire VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library datasheet
- get in contact with VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library Supplier
SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library IP
- SMIC 0.13um General Process, 1.2V/2.5V Standard I/O Library
- SMIC 0.13um 1.2V/2.5V ANALOGIO_05 IO Library
- VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V ANALOGIO_DUP_05 IO Library
- VeriSilicon SMIC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
- VeriSilicon SMIC 0.11um 1.2V/3.3V ANALOGIO_DUP_05 IO Library
- SMIC 130nm G SSTL2 I/O library