VeriSilicon SMIC 0.13μm SSTL2/SSTL3 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13μm Logic 1P6M Salicide 1.3V/3.3V process. This library is fully compliant with JESD8-8 Stub Series Terminated Logic for 3.3V (SSTL3), JESD8-9B Stub Series Terminated Logic for 2.5V (SSTL2) and JESD79E DDR SDRAM specification.
- SMIC 0.13μm Logic 1P6M Salicide 1.2V/3.3V process
- Support SSTL3 class1&class2 and SSTL2 class1
- Receiver and driver operation frequency: up to 200MHz
- Power down mode in input buffer
- Power on sequence control mode
- Programmable driver strength: SSTL3 class1&2 or SSTL2 class1
- 2kv/200v typical HBM/MM ESD immunity