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Very Small Form-Factor Division Core
This is a configurable reciprocal DSP core for signal processing application on programmable logic devices.
The core operates on streamed data which is reciprocated (inverse value calculated) via a non-traditional, intelligent, innovative design. After an initial output delay equal to the bit width of the input plus 4 clock cycles, the output is also streamed out at a rate of one result per clock cycle.
This DSP engine is written in VHDL, capable of being used on any FPGA/ASIC architecture.
The core operates on streamed data which is reciprocated (inverse value calculated) via a non-traditional, intelligent, innovative design. After an initial output delay equal to the bit width of the input plus 4 clock cycles, the output is also streamed out at a rate of one result per clock cycle.
This DSP engine is written in VHDL, capable of being used on any FPGA/ASIC architecture.
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