Very Small Form-Factor Division Core
The core operates on streamed data which is reciprocated (inverse value calculated) via a non-traditional, intelligent, innovative design. After an initial output delay equal to the bit width of the input plus 4 clock cycles, the output is also streamed out at a rate of one result per clock cycle.
This DSP engine is written in VHDL, capable of being used on any FPGA/ASIC architecture.
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Division IP
- Divide-by-N, up to 3GHz, Programmanble Division Number - GlobalFoundries 40nm
- Divide-by-N, up to 3GHz, Programmanble Division Number
- RF SPDT Switch from 10-30 GHz used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation
- RF SPDT Switch from 20-40 GHz used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation
- RF SP3T Switch used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation
- RF SPDT Switch from 20-40 GHz used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation