Voltage Domain Interfacing Cells for use between power domains using core transistors.
VESA Display Stream Compression (DSC) IP Core
The DSC encoder or decoder has a rich set of parameterizations to enable an optimal customer implementation. User parameterized number of slices enables targeting of different transport protocols such as MIPI or DisplayPort.
The Bitec DSC Implementation has a rich set of parameters to allow for a optimized and customized solution. Complete control of color depth, image geometry and prediction methods are available to reduce resource usage and boost performance.
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Block Diagram of the VESA Display Stream Compression (DSC) IP Core

VESA DSC IP
- VESA DSC Encoder
- VESA DSC (Display Stream Compression) 1.2a Video Encoder
- VESA DSC (Display Stream Compression) 1.2a Video Decoder
- MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- VESA DSC ENCODER IP