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VESA Display Stream Compression (DSC) IP Core
Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resolution video technologies. Bitec offer a highly optimized implementation of the DSC 1.2a as a stand-alone component and/or an integrated component to the Bitec DisplayPort 1.4 and HDMI 2.1 IP Cores.
The DSC encoder or decoder has a rich set of parameterizations to enable an optimal customer implementation. User parameterized number of slices enables targeting of different transport protocols such as MIPI or DisplayPort.
The Bitec DSC Implementation has a rich set of parameters to allow for a optimized and customized solution. Complete control of color depth, image geometry and prediction methods are available to reduce resource usage and boost performance.
The DSC encoder or decoder has a rich set of parameterizations to enable an optimal customer implementation. User parameterized number of slices enables targeting of different transport protocols such as MIPI or DisplayPort.
The Bitec DSC Implementation has a rich set of parameters to allow for a optimized and customized solution. Complete control of color depth, image geometry and prediction methods are available to reduce resource usage and boost performance.
Features
- Supports Versions 1.1, 1.2 and 1.2a
- Supports RGB and YCbCr color spaces
- 1-to-8 slice support
- Optional support for Block Prediction
- Parameterized video geometry
- 4:4:4, 4:2:2 and 4:2:0 color spaces
Deliverables
- The Bitec DSC IP Core is delivered with testbenches, documentation and example implementations for DisplayPort and HDMI 2.1.
Block Diagram of the VESA Display Stream Compression (DSC) IP Core
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VESA DSC
- VESA DSC (Display Stream Compression) 1.1 Video Encoder
- VESA DSC (Display Stream Compression) 1.1 Video Decoder
- VESA DSC (Display Stream Compression) 1.2a Video Encoder
- VESA DSC (Display Stream Compression) 1.2a Video Decoder
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DisplayPort 1.4 TX IP Subsystem for Xilinx FPGAs