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VESA DisplayPort 1.4 TX IP Subsystem for Xilinx FPGAs
Features
- Complete DisplayPort™ 1.4 Transmitter solution with support for VESA Display Stream Compression (DSC)
- Fully compliant with the DisplayPort 1.4a Standard
- Including the DSC slices per line requirements
- Supports up to 4 lanes at HBR3 rate (8.1 Gbits/sec)
- Configurable maximum display resolution up to 8K (FUHD) 60fps in RGB 444
- All color spaces supported by DSC v1.2a and component bit depth up to 12 bits
- Support for Xilinx® UltraScale™ and UltraScale+™ devices
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Block Diagram of the VESA DisplayPort 1.4 TX IP Subsystem for Xilinx FPGAs
DisplayPort IP
- USB 3.1/DisplayPort 1.4 IP Subsystem Solution
- DisplayPort 1.4a IP Core
- DisplayPort 1.4a Transmitter Link Controller
- DisplayPort 1.4a Receiver Link Controller
- Content Protection (HDCP) 2.2/2.3 embedded security modules (ESMs) for HDMI, DisplayPort, and USB 3.x Type-C interfaces
- PHY IP for DisplayPort/Embedded DisplayPort TX