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Process Detector (For DVFS and monitoring process variation), TSMC N3
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VESA DisplayPort 2.0 FEC RX
The DisplayPort Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 2.0 specification. Forward Error Correction is required to ensure low bit error rate at UHBR link rates and glitch-free Display Stream Compression (DSC) bitstream transport.
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Block Diagram of the VESA DisplayPort 2.0 FEC RX IP Core
DisplayPort IP
- USB 3.1/DisplayPort 1.4 IP Subsystem Solution
- DisplayPort 1.4a IP Core
- DisplayPort 1.4a Transmitter Link Controller
- DisplayPort 1.4a Receiver Link Controller
- Content Protection (HDCP) 2.2/2.3 embedded security modules (ESMs) for HDMI, DisplayPort, and USB 3.x Type-C interfaces
- DisplayPort Transmitter & Receiver