MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
VESA DSC (Display Stream Compression) 1.2b Video Decoder
Features
- VESA DSC 1.2b compliant
- Supports all DSC 1.2b mandatory encoding mechanisms
- MMAP, BP, MPP, and ICH
- Input buffering compatible with transport stream over video interfaces
- Configurable maximum display resolution
- Up to 4K (4096x2160), 5K (UHD+), and 8K (FUHD)
- 8, 10, 12, 14, and 16 bits per video component
- YCbCr and RGB video output format
- 4:4:4, 4:2:2, and 4:2:0 native coding
- Resilient to bitstream corruption
- 3 pixels / clock internal processing architecture in 4:4:4
- 6 pixels / clock internal processing architecture in 4:2:2 and 4:2:0
- Parameterizable number of parallel slice decoder instances
- (1, 2 or 4) to adapt to the capability of the technology and target display resolutions used
- Optional DSC features can be disabled to improve area
- 100% verification coverage based on UVM environment
- Verified against the VESA DSC 1.2b C model using a comprehensive test image library
- Backward compatible with DSC 1.1
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Block Diagram of the VESA DSC (Display Stream Compression) 1.2b Video Decoder
VESA DSC Video Encoder IP
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