The VHDL Reference CAN is intended for semiconductor designers/manufacturers who want to build their own implementation of a CAN or CAN FD device using VHDL as a hardware description language.
The test bench supplied with this VHDL Reference CAN assures the conformity of the CAN Protocol Controller part of an user-defined implementation with ISO 11898-1:2015.
- Supports CAN and CAN FD according to ISO 11898-1:2015
- Flexible test bench environment
- Simulates entire CAN bus system (number of nodes defined by user)
- Test program set can be extended by user
- Run time information stored in trace file
- Generation of pattern files supported
- Most widely spread tool for verification of VHDLbased CAN implementations
- Reduces risk to fail CAN conformance test
- Detailed User’s Manual
- Example of an implementation for fast start-up
- Well documented source code
- Tested with Synopsys VSS, Mentor Graphics QuickHDL, Mentor Graphics ModelSim
- Prepared for porting to other VHDL simulators
Block Diagram of the VHDL Reference CAN IP Core