Video De-Interlacer converts the interlaced video signals into non-interlaced signals. This core separates the intermeshed odd and even fields of the NTSC/PAL frames output by the video decoder, into a combined, sequential de-interlaced frame, in order to display on LCD.
- Supports PAL or NTSC video mode
- RAM like memory interface with separate read and write controls
- Fully stallable interfaces on both input and output
- Simple design makes it easier to integrate in many FPGA families
- Video and image processing applications in Aerospace and Defense, Automotive, Broadcast, Consumer, Industrial and Medical applications
Block Diagram of the Video DeInterlacer IP Core