The Xilinx® LogiCORE™ IP Video Frame Buffer Read and Video Frame Buffer Write cores provide high-bandwidth direct memory access between memory and AXI4-Stream video type target peripherals which support the AXI4-Stream Video protocol. The cores can take AXI4 Streams and unpack the data to formats supported by Zynq US+ Video Codec Unit (VCU). The primary use case for these cores is with Zynq US+ VCU albeit it can be used for generic Frame writes and read functions. Users are requested to review AXI Video DMA Controller before choosing the appropriate Video DMA for their use case.
- AXI4 Compliant
- Specifically design to support Zynq US+ Video Codec Unit (VCU) use cases: AXI4 compliant streams to AXI memory mapped and supports pixel unpacking and packing of data for use with Zynq US+ EV device’s VCU
- Streaming Video Format support for: RGB, YUV 444, YUV 422, YUV 420
- Memory Video Format support for: RGBX8, YUVX8, YUYV8, RGBX10, YUVX10, Y_UV8, Y_UV8_420, RGB8, YUV8, Y_UV10, Y_UV10_420, Y8, Y10
- Supports 8 and 10-bits per color component on stream interface and memory interface
- Supports spatial resolutions from 64 x 64 up to 8192 x 4320
- Supports up to 4K60 performance