The VSC-4KX is a high quality polyphase scaler for up/down/cross conversion between video formats up to 4K resolution. The VSC-4KX up converts SD/HD video signals to 4K resolution and down converts 4K inputs to SD or HD. In addition, the VSC-4KX can cross convert a 4K input to a 4K output with up/down scaling. Compatibility with most interface types including SDI (2SI and Square Division), DisplayPort and HDMI is provided. When not processing 4K signals, the VSC-4KX may be used to process up to 4 independent HD channels. The scaler may be used in conjunction with the VPC-1 Video Processor and Deinterlacer IP core or with any other customer or third party IP. Support for any scale factor allows full screen display of any input as well as arbitrary resizing for PIP and multiviewer applications. In addition, the core includes a number of Verilog parameters that allow it to be tailored at build time to satisfy specific requirements.
The VSC-4KX is available with complete Verilog source code, Verilog test bench and bit-accurate C models as part of the license. Integration and programming guidelines are also included backed up by expert technical support.
A VSC-4KX reference design is available for standard development kits from Xilinx and Altera for demonstration and evaluation purposes. The design includes a built-in user interface with embedded OSD to simplify access to key features of the IP. In addition to simplifying the evaluation of the VSC-4KX IP core, the design also serves as a template for customer application development.
- Any input <= 4096x2160p scaled to any output <= 4096x2160p
- Compatible with most interface types including SDI (2SI and Square Division), DisplayPort and HDMI
- Conversion between interface types
- Can process 4 independent HD channels
- High quality polyphase scaling
- Invisible seams between tiles
- Dynamic resizing and aspect ratio conversion (ARC) without artifacts
- Region-of-Interest (ROI) scaling
- Supports all frame rates up to 60 Hz
- 8/10/12-bit 4:2:2 or 4:4:4 processing
- Seamless interface to VPC-1 deinterlacer
- Dynamically loadable coefficients for flexible image quality
- Optional image sharpening
- Build Time Options
- 4:2:2 or 4:4:4 data path
- 8, 10 or 12-bit data path precision
- Number of taps, number of phases, coefficient precision
- 2 or 4 pixel parallel processing for 600 MPixel/s throughput with 150 MHz or 300 MHz clock frequency.
- Support for both Xilinx and Altera devices
- Synthesizable Verilog RTL source code (encrypted or unencrypted as per license agreement)
- Verilog testbench
- Bit-accurate C model
- Verification test suite
- Product documentation
- Integration guidelines
- Integration support