Viterbi Encoder, Viterbi Decoder

Features

• This is a high throughput viterbi decoder IP core.
• The design is fully parallel and pipelined. The code rate is 1/2.
• The constraint length is 7. The two generator polynomials are 133 and 171.
• This is the core of lots of industry standard vitervi decoders.
• Additional puncture and depuncture circuit can be used to get different code rates.
• The inputs are 4-bit soft inputs and the traceback length is 64.

Deliverables

• The Viterbi decoder is available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification.

• see the entire Viterbi Encoder, Viterbi Decoder datasheet
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