|
Status
|
Item
|
Offers
|
Posted
|
|
Physical design implementation of “ARP Block-4” module at 28nm “CHIPTOP” module at 90nm
|
2 |
Apr. 26, 2022 |
|
WiFi 6 TRX
|
3 |
Apr. 24, 2022 |
|
|
Software/EDA Tool - Processor Architecture Simulator
|
4 |
Mar. 21, 2022 |
|
|
LDO (TSMC 0.13um RFCMOS)
|
4 |
Mar. 15, 2022 |
|
|
TSMC 65nm RFCMOS / Mixed mode ADC 12bit 10Mbps
|
5 |
Mar. 15, 2022 |
|
|
D/A Converter
|
3 |
Mar. 11, 2022 |
|
|
MCH EMC interface to AXI
|
2 |
Mar. 07, 2022 |
|
|
Turbo Decoder for HomePlugAV
|
3 |
Mar. 04, 2022 |
|
|
TSMC 65nm RFCMOS / Mixed mode ADC 12bit 100Khz ~ 100Mbps
|
3 |
Feb. 16, 2022 |
|
|
sdio3.0 controller
|
5 |
Feb. 15, 2022 |
|
|
TSMC 65nm RFCMOS / Mixed mode ADC 12bit 100Khz ~ 1Mbps
|
4 |
Feb. 10, 2022 |
|
|
12bit ADC IP
|
7 |
Feb. 10, 2022 |
|
|
TSMC 90LP eFlash, ADC & DAC
|
6 |
Jan. 31, 2022 |
|
|
ADC 12bit 3-5 MSPS, 1 channel, SFDR 60 db
|
5 |
Jan. 31, 2022 |
|
|
TSMC 65nm RFCMOS / Mixed mode ADC 12bit 100Khz
|
6 |
Jan. 29, 2022 |
|
|
DFI to Xilinx MIG interface bridge IP
|
0 |
Dec. 15, 2021 |
|
|
SD/HD video image stabilization
|
2 |
Nov. 12, 2021 |
|
|
DigRF controller
|
1 |
Oct. 28, 2021 |
|
|
Sigma Delta ADC for TSMC 55ULP eFlash
|
1 |
Oct. 14, 2021 |
|
|
eZ80 core
|
1 |
Sep. 26, 2021 |
|
|
8-bit, 10GS/s ADC
|
11 |
Sep. 20, 2021 |
|
|
RS422 receiver+Digital isolator+Can receiver and transceiver
|
2 |
Sep. 01, 2021 |
|
|
SGMII SerDes for UMC 40LP
|
3 |
Aug. 31, 2021 |
|
|
eFLASH
|
3 |
Aug. 16, 2021 |
|
|
10/100/1000 Ethernet BASE-T PHY for TSMC 28HPC+
|
5 |
Aug. 05, 2021 |
|
|
roce v2 ip
|
5 |
Jul. 31, 2021 |
|
|
Ethernet IP optic+copper for Altera
|
0 |
May. 28, 2021 |
|
|
USB2.0 controller IP,SSP,SSI
|
6 |
May. 24, 2021 |
|
|
Ethernet PHY on SMIC Process
|
4 |
May. 06, 2021 |
|
|
MIPI D-PHY RX V1.2
|
5 |
Apr. 05, 2021 |
|
|
GRETH - 10/100 Mbit Ethernet MAC
|
2 |
Mar. 30, 2021 |
|
|
28 nm PLL
|
7 |
Mar. 04, 2021 |
|
|
Parallel RGB to UVC1.5
|
3 |
Feb. 16, 2021 |
|
|
sLVDS to MIPI
|
3 |
Feb. 15, 2021 |
|
|
Image Signal Processor (ISP)
|
6 |
Feb. 13, 2021 |
|
|
PCIe 5.0 PHY with CXL support for TSMC 28/22/16/12
|
2 |
Feb. 02, 2021 |
|
|
28G Multi-SerDes for TSMC 28HPC+
|
3 |
Jan. 20, 2021 |
|
|
PLL details GNSS
|
10 |
Dec. 26, 2020 |
|
|
Camera Link receiver
|
5 |
Dec. 08, 2020 |
|
|
PLL IP in TSMC 28nm HPC+
|
7 |
Dec. 07, 2020 |
|
|
ADC
|
10 |
Dec. 07, 2020 |
|
|
SAR ADC
|
5 |
Dec. 03, 2020 |
|
|
SRAM SINGLE PORT
|
7 |
Dec. 01, 2020 |
|
|
MRAM IP
|
3 |
Nov. 25, 2020 |
|
|
MTP (EEPROM) for TSMC 40ULP eFlash / 55ULP eFlash / 90ULP eFlash
|
3 |
Oct. 19, 2020 |
|
|
16 ... 20 bit Sigma Delta ADC, TSMC 55ULP eFlash
|
3 |
Sep. 22, 2020 |
|
|
USART core with data validation logic
|
4 |
Sep. 20, 2020 |
|
|
18 ... 20 bit Sigma Delta ADC, 1 ... 5 MSPS, TSMC 65GP
|
4 |
Sep. 18, 2020 |
|
|
MCU system IP
|
8 |
Sep. 12, 2020 |
|
|
V-7 Series FPGA 40G Ethernet IP
|
6 |
Aug. 11, 2020 |
|
|
Buck regulator
|
7 |
Jul. 29, 2020 |
|
|
LDPC coder/decoder
|
3 |
Jul. 08, 2020 |
|
|
MIPI D-PHY v2.0 or higher
|
6 |
Jul. 01, 2020 |
|
|
MIPI Incuding PHY etc, up to 2GB, 4 lanes on HV process (~20v)
|
9 |
May. 20, 2020 |
|
|
MIPI
|
11 |
May. 19, 2020 |
|
|
EEPROM IP
|
3 |
Apr. 14, 2020 |
|
|
LDDR SDRAM controller
|
1 |
Mar. 06, 2020 |
|
|
HDMI 2.1 Rx and Tx
|
6 |
Mar. 05, 2020 |
|
|
10 BaseT PHY
|
3 |
Mar. 02, 2020 |
|
|
22nm efuse @ TSMC
|
5 |
Feb. 24, 2020 |
|
|
High speed ADC & DAC
|
21 |
Feb. 12, 2020 |
|
|
5V TSMC 40nm LP/ULP Comparator/DAC (8bit) with ANMUX
|
2 |
Dec. 22, 2019 |
|
|
5V TSMC 40nm LP/ULP 12bit SAR ADC
|
6 |
Dec. 21, 2019 |
|
|
5V TSMC 40nm LP/ULP EMF IO
|
2 |
Dec. 13, 2019 |
|
|
High quality ISP, low light performance, color fidelity, motion artifacts, detail extraction
|
2 |
Dec. 04, 2019 |
|
|
10,100,1000M Ethernet MAC IP
|
5 |
Nov. 26, 2019 |
|
|
SDI PHY and controller IP for ASIC
|
2 |
Nov. 15, 2019 |
|
|
Ethernet 10/100 BASE-T PHY for TSMC 90nm or 65nm
|
3 |
Oct. 29, 2019 |
|
|
SDIO,SD memory, EMMC combo IP
|
5 |
Oct. 18, 2019 |
|
|
SGMII PHY
|
1 |
Sep. 26, 2019 |
|
|
G.722 codec IP
|
1 |
Sep. 05, 2019 |
|
|
pcie endpoint soft ipcore for FPGA and pcie to pci birdge soft ipcore for FPGA
|
4 |
Jul. 24, 2019 |
|
|
Adaptive Digital Pre-Distortion, linear and non-linear
|
3 |
Jul. 08, 2019 |
|
|
PLL for UMC40LP
|
5 |
Jul. 05, 2019 |
|
|
ISDB-T BTS REMUX
|
3 |
Jul. 01, 2019 |
|
|
AFDX-ARINC 665 IP core for XILINX/INTEL FPGA
|
3 |
Jun. 27, 2019 |
|
|
JESD204C PHY Rx and Tx
|
7 |
Jun. 21, 2019 |
|
|
SAS initiator IP
|
2 |
Jun. 19, 2019 |
|
|
1000M Ethernet PHY
|
0 |
Jun. 13, 2019 |
|
|
Erasure code accelerator
|
4 |
Jun. 12, 2019 |
|
|
I3C Master for FPGA test environment
|
14 |
May. 15, 2019 |
|
|
DDR 3/4 PHY and controller
|
2 |
Apr. 29, 2019 |
|
|
QSGMII Controller/Converter for FPGA
|
2 |
Apr. 25, 2019 |
|
|
JESD204B Tx
|
9 |
Apr. 22, 2019 |
|
|
16 bits ADC - Clock frequency 20 MHz - supply voltage 3.3V
|
8 |
Apr. 03, 2019 |
|
|
PLL
|
9 |
Feb. 19, 2019 |
|
|
DCDC
|
3 |
Feb. 19, 2019 |
|
|
LPDDR4(x) PHY/IO
|
9 |
Jan. 23, 2019 |
|
|
MIPI RFFE Vers 2.1 Slave
|
0 |
Jan. 07, 2019 |
|
|
interface IPs
|
5 |
Dec. 26, 2018 |
|
|
12-bit 1-channel ADC
|
11 |
Dec. 11, 2018 |
|
|
IO and library
|
5 |
Dec. 04, 2018 |
|
|
Viterbi Decoder
|
11 |
Nov. 07, 2018 |
|
|
System Memory Management Unit (SMMU) - 32 bits
|
8 |
Oct. 25, 2018 |
|
|
Multipoint LVDS (M-LVDS) IP (Silicon-Proven in TSMC TSMC 28nmHPC/22nmULP process)
|
7 |
Oct. 25, 2018 |
|
|
CAN BUS 2.0B
|
4 |
Oct. 14, 2018 |
|
|
32bit fast embedded RISC CPU
|
8 |
Oct. 08, 2018 |
|
|
IEEE 802.11.AC
|
9 |
Oct. 07, 2018 |
|
|
SERDES for 10 GBPS Ethernet
|
9 |
Sep. 27, 2018 |
|
|
Video converters
|
2 |
Sep. 10, 2018 |
English
