The PLL operating voltage is from 0.6volts to 1.1 volts.
-40C to 85C`
M= 8 bits; N= 8bits
TSMC 40ULP. The PLL shall require <= 4LM
Input frequency range
Input frequency <4MHz
Maximum loop frequency
Power management features
The PLL shall be capable of three power modes:
- Operating mode;
- Idle mode: In this mode, the PLL clock output will be gated diabling current flow in the output digital stage. In this mode, the clock output will be held LOW.
- Sleep mode – in this mode, all DC paths to ground shall be disabled
The PLL shall be glitchless in switching frequencies, and switching among the power management states.
PLL shall be capable of locking within 100 clock cycles.
IP Model deliverables
.lef, .verilog, gdsii, integration guide, test guide,
The PLL testability shall be compatible with JTAG test port control. In addition, the PLL shall have a bypass mode.