Functionality
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PLL for UMC40LP (RVT, HVT only)
fin = 4 ... 33.3MHz (ideally: 4 ... 8MHz)
fout = 800MHz (for LPDDR4 1600)
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External compatibility and integration requirements
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min typ max unit
Supply voltage 1.06 1.1 1.17 V
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Timing or Performance requirements
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min typ max
tCK(avg)= 1/800Mhz 1.25 ns
Absolute High clock pulse width
tCH(abs) 48% 50% 52% tCK(avg)
Absolute Low clock pulse width
tCL(abs) 48% 50% 52% tCK(avg)
Clock period jitter tJIT(per)-2% - 2% tCK(avg)
Clock period jitter tJIT(per)-25 - 25 ps
Maximum Clock Jitter between consecutive cycles
tJIT(cc) - - 50 ps
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Technology Requirements
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UMC40LP, RVT and HVT only
Metal stack: 1P6M1T1U + 14.5kA Al RDL
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Availability Timing
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E/Sep 2019
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Quality requirement
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Automotive
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Business Scheme Requirement
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License w/o royalties, 2 uses
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