Functionality
|
PLL for UMC40LP (RVT, HVT only)
fin = 4 ... 33.3MHz (ideally: 4 ... 8MHz)
fout = 800MHz (for LPDDR4 1600)
|
|
External compatibility and integration requirements
|
|
min typ max unit
Supply voltage 1.06 1.1 1.17 V
|
|
Timing or Performance requirements
|
|
min typ max
tCK(avg)= 1/800Mhz 1.25 ns
Absolute High clock pulse width
tCH(abs) 48% 50% 52% tCK(avg)
Absolute Low clock pulse width
tCL(abs) 48% 50% 52% tCK(avg)
Clock period jitter tJIT(per)-2% - 2% tCK(avg)
Clock period jitter tJIT(per)-25 - 25 ps
Maximum Clock Jitter between consecutive cycles
tJIT(cc) - - 50 ps
|
|
Technology Requirements
|
|
UMC40LP, RVT and HVT only
Metal stack: 1P6M1T1U + 14.5kA Al RDL
|
|
Availability Timing
|
|
E/Sep 2019
|
|
Quality requirement
|
|
Automotive
|
|
Business Scheme Requirement
|
|
License w/o royalties, 2 uses
|
|
English
(mail
this request to a colleague) 