Semiconductor IP: MIPI D-PHY v2.0 or higher

MIPI D-PHY v2.0 or higher

Item #2013

	Posted	Jul. 01, 2020

	# of Offers	6

	Status

		(mail this request to a colleague)

Customer assumes all responsibility for listing this item.

Request Description

Functionality

Supports MIPI Alliance Specification for D-PHY Version 2.0 or higher
Backward compatible with MIPI Specifications for D-PHY v1.2 and v1.1
Consists of 1 Clock lane and 4 Data lanes
Embedded high performance, highly programmable, PLL
PLL supports SSC mode, Fractional mode, and Integer mode
Supports both high speed and low-power modes
Up to 4.5 Gbps data rate per lane with Deskew calibration
Supports High Speed TX De-emphasis Equalization
Supports High Speed RX CTLE
10 Mbps data rate in low-power mode
Low power dissipation
Testability support including internal loopback
Calibrator for resistance termination

External compatibility and integration requirements

CSI-2, CCS, and DSI-2 that is compatible with D-PHY v2.0 or higher

Technology Requirements

CMOS Automotive

Quality requirement

Verified

Business Scheme Requirement

Automotive

Customer Profile

Position of the person having emitted the request		R&D Engineering

Corporation Profile
	End Product	TV/Satellite/Broadcast Equipment
	Gross Annual Dollar Sales	Under $10 Million
	Size of his organization at this location	6 - 19
	Size of his organization in entire company	6 - 19
	Location	Seongnam, Gyeonggi-do, Korea, Republic of

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