Functionality
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Memory Size: 16384 words x 128 bits
User Mode
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Pin Direction Description
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XADR[8:0] I X address input, access rows, XADR[3:0] select one row
row within a page of main memory block or
information block.
YADR[4:0] I Y address input, access data within a row.
DIN[127:0] I Data input bus.
DOUT[127:0] O Data output bus.
XE I X address enable, all rows are disabled when XE=0.
YE I Y address enable, YMUX is disabled when YE=0.
SE I Sense amplifier enable.
IFREN I Enable information block. (Notes 4)
ERASE I Defines erase cycle.
MAS1 I Defines mass erase cycle, erase whole block.
PROG I Defines program circle.
NVSTR I Defines non-volatile store cycle.
PDM_IO I PDM_IO=VDIO when VDD is not ready or not available
for flash IP.
SLM I Sleep mode enable. SLM=VDD turns off all bias
circuit in Flash IP.
LVE I Low voltage read enable (LVE=VDD) when
0.81V<= VDD <0.99V
PWRRDY_IO I Power ready, PWRRDY_IO=VDIO when power is ready.
PWRRDY_IO=VSS if power down or power lost.
VDIO I Power supply (Notes 3)
VDD I Power supply (Notes 2)
VSS I Ground (Notes 2)
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