Warping Engine IP block for image transformation, HUDs and fish-eye correction
The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Altera Avalon bus interface at different bus width (e.g. 32, 64, 128 bits).
View Warping Engine IP block for image transformation, HUDs and fish-eye correction full description to...
- see the entire Warping Engine IP block for image transformation, HUDs and fish-eye correction datasheet
- get in contact with Warping Engine IP block for image transformation, HUDs and fish-eye correction Supplier
Video Input IP
- Versatile Video Input - frame grabber
- Customizable Video Input Controller with color space conversion
- Camera/HDMI Video Input Interface
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- 2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver