MIL-STD-1553B Notice 2 Bus Controller, Remote Terminal, Bus monitor IP Core for FPGA and ASIC Devices The BRM1553D IP Core is suitable for any Mil-Std-1553 implementation. The core incorporates a backend logic that arranges the messages in a predefined memory and registers structure, which simplifies the interface between the 1553 bus and the local CPU. The BRM1553D core provides DDC® Enhanced MINI-ACE® compatiability to support exsisting software implementations. The MIL-STD-1553 IP can be licensed with the cyber security or wiring fault capabilities out of the box.