Sensor fusion solutions for augmented and virtual reality, robotics, motion controllers, and IoT
Wide-band Analog-to-Digital Converter
The ADC includes two internal power supply regulators (LDO) for the analog part:
- A 1.1v LDO with external decoupling capacitor to reach a high power rejection ratio
- A 1.5v LDO with internal capacitor for the input buffer and biasing.
The digital part is supplied by the external 1.0V.The digital corrector receives the 16 sub-ADC 12b outputs and delivers 14b for each output. Hence, the output data are organized in 16x14b–buses clocked at 270MHz (Fs/16). Each bus gives the data coming from a specific sub-ADC in a 2’s complemented format (range is [-2N-1; 2N-1-1]). A data ready clock is provided at 270MHz (Fs/16).
Features
- 14-bit Time-Interleaved Pipeline ADC
- 4.32GSps Sampling Rate
- 60dBFS SNR (9.7 ENOB) with 54MHz<Fin<1794MHz
- External AC coupling for the input signal
- Two power supplies: 1.8V for analog and 1.0V for digital compensation
- 1.0Vpp differential full-scale input
- Buffered analog inputs
- Input signal bandwidth: 54MHz to 1794MHz
- Power down mode
- 16x14bits data output at 270 MHz (4.32GHz/16)
- Data ready output at 270MHz
- Twos complement data format
- Size:Under NDA
- Power Consumption:
- Analog: 218-460 mW on 1.8V supply
- Digital: 276-491 mW on 1.0V supply
- Total: 495-951 mW
- Technology: Under NDA
- Device types: GO1 (LVT, RVT), GO2 (31Ang, 1V8), MIM Capacitor
- DK2.5d
Deliverables
- Detailed Specification and Integration guide
- LEF abstract
- GDSII layout and Mapping files
- LVS compatible Netlist
- Verilog-A Model
Block Diagram of the Wide-band Analog-to-Digital Converter IP Core
View Wide-band Analog-to-Digital Converter full description to...
- see the entire Wide-band Analog-to-Digital Converter datasheet
- get in contact with Wide-band Analog-to-Digital Converter Supplier