The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_HOST_GTHE4 IP is compliant with Serial ATA III specification and signaling rate is 6Gbs. The LDS_SATA3_HOST_GTHE4 IP is fully synchronous with system frequency (Clock_sys) at 150MHz in case of 6Gbs speed selection. The source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.