The XPS BRAM Interface Controller is a Xilinx IP module that incorporates a PLB V4.6 (Processor Local Bus) interface. This controller is designed to be byte accessible. Any access size (in bytes) up to the parameterized data width of the BRAM is permitted. The XPS BRAM Interface Controller is the interface between the PLBV46 and the bram_block peripheral.
- PLB V4.6 bus interface with byte enable support
- Supports up to three transfer types
- Used in conjunction with Xilinx EDK generated bram_block peripheral to provide total BRAM memory solution