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XPS IIC Bus Interface
Included in EDK at no additional charge starting in EDK9.2i
This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the XPS IIC module. It provides a low speed, two wire, serial bus interface to a large number of popular devices.
This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the XPS IIC module. It provides a low speed, two wire, serial bus interface to a large number of popular devices.
Features
- Master or slave operation
- Multi-master operation
- Software selectable acknowledge bit
- Arbitration lost interrupt with automatic mode switching from master to slave.
- Calling address identification interrupt with automatic mode switching from master to slave
- START and STOP signal generation/detection
- Repeated START signal generation
- Acknowledge bit generation/detection
- Bus busy detection
- Fast mode 400 KHz operation or standard mode 100 KHz
- 7 bit or 10 bit addressing
- General call enable or disable
- Transmit and receive FIFOs - 16 bytes deep
- Throttling
- General purpose output, 1 bit to 8 bits wide
- Dynamic Start/Stop generation
View XPS IIC Bus Interface full description to...
- see the entire XPS IIC Bus Interface datasheet
- get in contact with XPS IIC Bus Interface Supplier
Embedded
- Customizable Embedded Multi-port PCIe Switch
- Embedded FPGA cores for TSMC 40LP/ULP
- ARC SEM110 Security Processor for Low Power Embedded Applications
- ARC SEM120D Security Processor with DSP for Low Power Embedded Applications
- Deeply embedded processor for deterministic real-time applications
- Ultra Low embedded SRAM
