The Xilinx Multi-Channel External Memory Controller (XPS MCH EMC) provides the control interface for external synchronous, asynchronous SRAM and Flash memory devices through the MCH or PLB interfaces. It is assumed that the reader is familiar with the PLB and MCH protocol.
- Connects as a 32-bit slave on PLB v4.6 bus of 32, 64 or 128 bits
- Can be used with PLB interface only or MCH interface only or in combination of both PLB and MCH interfaces
- Supports multiple (up to 4) external memory banks
- Supports single-beat and burst transactions