In a multi processor environment the processors share common resources. The mutex provides a mechanism for mutual exclusion to enable one process to gain exclusive access to a particular resource. XPS Mutex core contains a configurable number of mutexes. Each of these can be associated with a 32-bit User configuration register to store arbitrary data.
- PLB interface is based on PLB v4.6 specification
- Configurable number of PLB interfaces from 1 to 8
- Configurable asynchronous or synchronous interface operation
- Configurable USER register
- Configurable number of mutexes
- Configurable CPUID width
- Configurable enhanced security through hardware identification support