The XPS Thin Film Transistor (TFT) controller is a hardware display controller IP core capable of displaying 256k colors. The XPS TFT controller connects as a master on the PLB V4.6 (Processor Local Bus with Xilinx simplification) and reads the video pixel data from PLB attached video memory. This core also connects as a slave to the PLB or DCR (Device Control Register) bus for the register access. This core is capable of configuring Chrontel CH-7301 DVI Transmitter Chip through I2C interface.
- Connects as 64-bit master on PLB V4.6 bus of 64 or 128 bits data width
- Connects as a 32-bit Slave on the DCR V2.9 bus or PLB V4.6 bus of 32, 64 and 128 bits data width
- Supports DCR daisy chain protocol
- Parameterizable TFT interface for 18-bit VGA or 24-bit DVI
- Supports 25 Mhz TFT clock for display resolution of 640x480 pixels at 60 Hz refresh rate
- Supports configuration of external Chrontel DVI Transmitter Chip through I2C interface
- Supports separate clock domain for PLB interface and TFT interface